This note is in group My FPGA pages. In this note I will try to find out what might be in FPGA design for me. And if so, how. Observe Standard Disclaimer.

Fold handling with Collapse-O-Matic plugin

I am using Collape-O-Matic (here) on many pages.

Typical fold

Intros

1st investigation: myStorm?

A year ago a friend told me don’t think about Xilinx because it is too expensive, and don’t use their vendor tools because they are bloated and slow. And he continued, have a look at myStorm Ice40 instead. I guess he simply stated that we were not in Xilinx’s audience. Finally, in comparison to Altera FPGAs the Ice40 is simpler and less powerful, but has the huge advantage of support by the opensource Yosys tool.

I therefore googled myStorm Ice40 and discovered a page that had been updated only 18 months ago (Feb2018) [2]. There, Folknology talks about BlackIce and the latest incarnation myStorm BlackIce II. I have no problem using old systems (old?), but I would still like something to be happening now, simply because I couldn’t do it alone.

(Altera is now a subsidiary of Intel. And  Xilinx → AMD)

Aside: retrospective

Now? Didn’t I take an exam in these matters once? LSI – konstruksjon og hjelpemidler (in Norwegian) or rather LSI – design and tools. At NTH, 1986 – 10 years after I graduated. (And after 40+ years in the industry I now, as retired, I am lucky enough to do some work for NTNU, here). The course was in 1983 (nineteen eighty three). Yes, the word VLSI had been invented then. The course book was Principles of CMOS VLSI Design: A Systems Perspective by N. Weste and Kamram Eshraghian [3] and we learned about Spice. Plus, I wrongly recollected: also some of the Verilog hardware description language (HDL).

This was at a time when Autronica (the company I always worked for) already in 1982-83 had had two VLSI chips designed for them. An address unit and a detector unit for their first addressable smoke detector (as addressable, a first – even worldwide). These chips were used for many years. As some guys at work did the specification and testing, the VLSI implementation was outsourced to SINTEF in Trondheim. I also recollect. The original colour paper printing that they used to show to people resides by me, at least for the time being. At some moment in time the alternative was the dustbin. (More about the Autronica chips at Notes from the vault – 0x03)

In the nineties I did some designs mostly using the ABEL HDL (where I had included test vectors) for some stray logic and bus connections for transputer and TMS320 DSP systems. In 1995 we updated an ABEL 1990 version into 6.1 at a price of 11000 NOK (around 1000 GBP) without blinking an eye. In all of the systems where we used this technology we were running occam, initially natively and later through the very functional SPOC occam-to-C translator. By not only digging in files, but also in leftover boxes I found the PC/104 (not called PC-104) board. I used (1) Atmel ATV750L Programmable Logic Device (PLD) with 20 sum terms, (2) AMDs PALCE22V10 Programmable Array Logic (PAL) with 10 macro cells and an AND array of 144*32 and (3) Lattice ispLSI2032E with 1000 PLD gates – with more than one on each board. They weren’t that big. I always liked it. But alas, that was all. The years passed and I did other things, mostly concurrent SW and schedulers. And nobody else at work did any VLSI, FPGA or PAL designs. (This board is also discussed in note 210, here).

But doing FPGA has always been a dream. Plus, some time getting a flavour of Verilog. Even getting a flavour my now down-the-line Xilinx and ALTERA – to me like remote stars since the early eighties.

2nd investigation: BlackIce Mx?

The myStorm page’s 18 months ageing all of a sudden was less of a problem when I discovered (but I can’t trace how) the myStorm IceCore board at GitHub [5] – also by Folknology. Github contains the IceCore Ice40 HX based modular core. The silk printing on the IceCore board says Copyright 2018, Alan Wood, @folknology, www.mystorm.uk. A name revealed. But I can not find any trace of this board at the silk print’s url. At the Twitter account he points to Folknology Labs [4] (that also mentions Folknology Club) – where the About takes me to a Tindie store that seems to be active now [6]. The BlackIce Mx is sold there, with the text myStorm BlackIce Mx is our 5th generation FPGA development board. In [10] I read that BlackIce Mx composition is based around a carrier and Core module, the carrier in this case is MixMod based and the initial bundled core is the new IceCore (The fastest Ice40 – HX). The silk printing on the BlackIce Mx board simply says Copyright 2018, Alan Wood.

«BlackIce Mx» = (IceCore + BlackIce Mx) @ BlackEdge

The above formula is not as recursive as it looks:

@folknology writes at myStorm forum (here) that BlackIce Mx is composed of a core (IceCore) and a carrier (BlackIce Mx [21]), these were built and designed to the BlackEdge standard. BTW ‘BlackIce Mx’ is commonly used to refer to the combination of these parts together which is a little confusing.. And @lawrie adds and BlackEdge is sometimes used to refer to the combination that includes the future ECP5 core, which is also confusing.

Also have a look at the BlackIce wiki [17] and BlackIce Mx eBook [18]. Plus the IceCore connections chapter (below).

3rd investigation: inside

I think it’s the Tindie store that has the best background info. By visiting several of the pages there I can read the very interesting story of how Al Wood et al even have been in China to lead the myStorm project for production ready boards. Impressing. Impressing also: the open source HW.

Since I am not in scope to understand the number of PIOs and logic cells, and since I haven’t even figured out what to make, I will concentrate on some other matters. Listing up:

• myStorm «BlackIce Mx» (named as such, containing the real BlackIce Mx plus the core BlackIce board) [10], residing on its BlackIce core board:
  • STM32F730 216MHz, 256KB Ram, 64KB Flash =
    Arm® Cortex®-M7 core (with floating point unit) [8]
  • ICE40HX4K FPGA 144 pins [9]

At first I mistook this for a ESP32 processor since I saw the 32 in there and did not think that any Arm chip naming included that. But no, this is an Arm proper. But I have seen both 200 and 216 MHz mentioned, not that it matters to me (right now?).

Pros and cons

Even if [31] would not be very relevant here, it’s a lot to learn from it! «11 Reasons You Should NOT use an FPGA for a Design, and Four Reasons You Should». Have a read!

How to develop with BlackIce boards

I am not certain how the BlackIce boards are developed. After having tried to find the very many loose ends I think I see some alternatives. This is after the necessary Verilog and Yosys SW is runnable in some way.

1. Single-line command based in Terminal
2. An editor alone (like the Atom)
3. Apio from the command line
4. An editor with a plug-in (Atom with the Apio plugin)
5. Icestudio visual editor

See myStorm forum Ads blackice MX on icestudio.

Download and building the tools

This is some of what I ended up with after these installs (even if NextPNR failed) (top and bottom application just to show the context):

Fig.1 – Screen cut of macOS Applications folder with IceStorm code installed

Enable XCODE command line tools log

Can I run the development tool on my Mac? I am in the process of selling my two USB scopes because the Mac support was lousy. I don’t want to be trapped again.

From [5]: As makers, we fell in love with IceStorm opensource Verilog toolchain back in 2015 [26] and wanted to create a best of class independent opensource hardware development board to fully use the IceStorm FPGA toolkit including Clifford Wolf’s amazing YOSYS [7] [25].

Now, the IceCore getting started page [12] shows how this development system may be installed on Macs. It is so updated that it even writes Installation prerequisites for macOS. OS X changed to macOS with Sierra (10.12) in 2016. This makes me somewhat relieved, even if a MyStorm page from 2018 did not..

I am running macOS High Sierra (10.13.6), thus being two revision behind Catalina 10.15 (19Nov2019).

Here is what I need to complete, according to [12].

1. Install Homebrew

   Homebrew install log

2. Enable XCODE command line tools

   bash-3.2$ xcode-select --install
   xcode-select: error: command line tools are already installed, use "Software Update" to install updates

3. Download libftdi0, python3 and gawk

   Download libftdi0, python3 and gawk install log

4. Download and install IceStorm

   Download and install IceStorm install log

5. Download and install Arachne-pnr

   Update 9Oct2019: I have learned that «for small projects, Arachne-pnr is fine, but it’s no longer under active development, and it doesn’t support more complicated things like multiple clock domains». That’s why NextPNR [28] is nice to have. I did this install twice since I forgot to start in the same directory as I started above. After this I deleted the /icestorm/arachne-pnr directory and ended up with /icestorm and /arachne-pnr in the same root: Download and install Arachne-pnr install log

   By the way, there is no man for arachne-pnr, but this helps:

   arachne-pnr --help

   however this does not help with the syntax of the pcf configuration file that it takes as input. Like what is the unit of 60 in this case:

   set_io clk 60

   To the rescue (here) is @lawrie’s code:

   set_io clk25 60 # Onboard 25Mhz oscillator

6. FAILED: Optional Installing NextPNR place&route tool

   This failed since it not find any cmake. I did finr a cmake.pro in a Qt directory I had, but I did not do anything to try to straiten this out. I will query about this anyhow.Update 9Oct2019: I have learned that this problem has been acknowledged by David Shah, the author of NextPNR [28].

   • First trial, but no cmake

     
     mymachine:IceStorm teig$ ls
     arachne-pnr	icestorm
     mymachine:IceStorm teig$ git clone https://github.com/YosysHQ/nextpnr nextpnr
     Cloning into 'nextpnr'...
     remote: Enumerating objects: 14351, done.
     remote: Total 14351 (delta 0), reused 0 (delta 0), pack-reused 14351
     Receiving objects: 100% (14351/14351), 5.70 MiB | 2.91 MiB/s, done.
     Resolving deltas: 100% (10526/10526), done.
     Checking connectivity... done.
     mymachine:IceStorm teig$ cd nextpnr
     mymachine:nextpnr teig$ cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local .
     -bash: cmake: command not found
     

   • Second trial, but no Boost

     As suggested in the myStorm forum, by @lawrie (here) why not just try brew install cmake? Good idea:

     The complete log is here 194_2019_11_21_cmake_and_nextpnr_install_log_failed.txt
     It contains three logs:

     ===1 #FILE Installing cmake ===
     ===2 #FILE Installing nextpnr ===
     ===3 #FILE CMakeOutput.log ===

     I think the problem is that Could NOT find Boost. How is that installed?

   • Installing Boost

     I followed the recipe on pyimagesearch, see Installing boost and boost-python on OSX with Homebrew. The log is at 194_2019_12_10_brew_install_boost_log.txt

   • Trying to install Boost again, not needed

     mymachine:bin teig$ brew install cmake
     Warning: cmake 3.15.5 is already installed and up-to-date
     To reinstall 3.15.5, run `brew reinstall cmake`

7. Ready-built nextpnr-ice40

   Update 11Dec2019: I have received a prebuilt macOS nextpnr-ice40 version (240 MB) from a user at the myStorm forum (AndyCap/Andrew Capon – thanks  lot!-). He also sent me the magic commands to have it run, so that all prerequisites would become installed:

   brew install boost boost-python3 qt5 eigen
   

   The log is at 194_2019_12_11_A_install_nextpnr_ice40_runs.txt and it runs!
   
   It reports that  «qt is keg-only»  which means that «the formula is installed only into the Cellar; it is not linked into /usr/local. This means most tools will not find it. We don’t do this for stupid reasons. You can still link in the formula if you need to with brew link.» (FAQ here). I’ll ask my man whether I need to make it available all over (answer: not needed).

   And then it’s a good idea to move the nextpnr-ice40 binary to /usr/local/bin, which should also be in the path. The last line would then also make sense (./ not needed):

   sudo cp ./nextpnr-ice40 /usr/local/bin
   echo $PATH
   nextpnr-ice40
   

   In /usr/local/bin there would also be several other relevant binaries by now: ice*, yosys* and arachne-pnr. I don’t know what all are for, but there are several.

   However Python still says 2.7.16 (so pip and python updates is not closed).

8. Downloading and installing Yosys install log

   Downloading and installing Yosys
   Aside: Observe Clifford Wolf’s lecture at YouTube [25].

Result of downloads and installs

As of 29Sep2019. An edited list:

Root: /Applications/IceStorm/ subdirectories:
drwxr-xr-x  arachne-pnr/  33.3MB
drwxr-xr-x  icestorm/    128.3MB
drwxr-xr-x  nextpnr/      20.0MB NOT SUCCESSFUL cmake
drwxr-xr-x  yosys/       710.7MB

Next with installs etc.

I will now take this to the forum to get som help on cmake [11]. Since nextpnr was optional I guess it’s kind of ok at the moment.

At the moment I have two IceCore boards! (19Nov2019)

Finally there is a tutorial that I would look forwards to try. Then later, perhaps, upload the design [12].

Not building from sources using apio and modules instead

Congratulations! Python 3.8.0 for macOS 10.9 or later was successfully installed.

brew install python3
brew upgrade python
brew link python
brew link --overwrite python

What to implement

Have a look in My IceCore notes.

Comments

I have mailed with several friends about this. I will try to summarise some here.

Comment 1 - Uwe Mielke (03-Oct-2019)

Comment 2 - RedPitaya

Comment 3 - SystemVerilog

Comment 4 - ECP5

Scratchpad 1

1. 10Oct2019: I tried to create a myStorm forum account, but I never saw the mail feedbacks to acknowledge it. In no mail folder of any type. I tried several times. I need to try again tomorrow. After getting some help I am now up and running as Aclassifier
2. Oct2019: But I found Verilog code from Simon Monk’s book: Programming FPGAs (by @lawrie) on the forum and immediately purchased the book Programming FPGAs: Getting Started with Verilog [13]. The forum post also pointed to a page where «someone had already converted a lot of examples to run on BlackIce» [14]. I can’t wait to get started! I have now received this book and if this isn’t a good start nothing is. I guess, since it’s from 2017 there is nothing in it about the BlackIce product range. The book mentions the below boards (or I may have found newer versions): see Simon Monk’s book (below)
3. myStorm people’s «yosys syntax» term – is it idiomatic for «Verilog syntax»? – is described as supporting Verilog-2005 which it supports «a large subset of» [7.1]. In the fantastic Yosys Manual (no date or version info in it) I find that:
   1. «Yosys can synthesize a large subset of Verilog 2005» (p28) and «The most important challenge is compliance with the HDL standards in question (in case of Verilog the IEEE Standards 1364.1-2002 and 1364-2005)»  in the Standards Compliance chapter (p20).
   2. If I search for SystemVerilog in the manual I find no discussion of this, but I find these spread lines, like «Only a small subset of SystemVerilog is supported» and «Full SystemVerilog support is only available via Verific.»
   3. So what of 2005 is not supported an what og SystemVerilog is perhaps something that will come to me in due course
   4. Update 19Dec2019, see query 1 at yosys tagged threads at StackExchange

IceCore connections

I guess it’s all in this myStorm thread by @lawrie: IceCore connections. It has these chapters:

• BlackEdge
• Mixmods (also see the two next chapters below)
• SPI connections
• I2C connections
• LEDs and buttons
• SWD pins
• UART pins
• HDMI connector
• SDRAM
• The RPi header

Also see a picture etc. of what I received at My IceCore notes (Unpacking).

Pmod Interface Specification

Digilent has defined (therefore first letter capitalised in the heading of this chapter) a standard for FPGA I/O connectivity:

The Digilent Pmod interface is used to connect low frequency, low I/O pin count peripheral modules to host controller boards. There are six-pin and twelve-pin versions of the interface defined. The six-pin version provides four digital I/O signal pins, one power pin and one ground pin. The twelve-pin version provides eight I/O signal pins, two power pins and two ground pins. The signals of the twelve-pin version are arranged so that it provides two of the six-pin interfaces stacked. [20]

Power is 3.3V. The FPGA community seems to use this a lot. The BlackIce Mx carrier board is no exception [21].

A typical Pmod board is Pmod 8LD: Eight High-brightness LEDs from Digilent (diagram here).

MixMods interface specification

MixMods has been defined by Alan Wood. He writes in the proposing document that

I have a none Pmod based carrier design (more later) aimed at more robust forms of expansion for robotics, automation and industrial applications, but it would be good to build on existing Pmods for general purpose development. [23]

In summary:

1. Observe the “BlackIce Mx” = (IceCore + BlackIce Mx) @ BlackEdge chapter (above)
2. Pinning, see BlackIceMx carrier/connection board, [21]
3. MixMods is based on the BlackEdge standard, [22]
4. Individual Pmods (12 single or 6 double). On BlackIceMx sockets MX1, MX2 and MX3, [24]
5. Some extra pins, these are the «mixed» pins. On BlackIceMx sockets COM/DBG and in between (non Pmod pins) on  MX1, MX2 and MX3
6. 5.0V power is also taken out on all BlackIceMx sockets if you solder across a jumper (default is not connected)

(Aside: I have queried about this at MixMods defined)

Use of third party designs

I need to find out about this. I have a feeling that both VHDL and Verilog reuse is by means of true source files. Like with the free Arm Cortex-M0 and M3 cores for Xilinx FPGAs project (2018, start here – an Arm/Xilinx shared effort) they seem to talk more about licences and soft IP, but also about source code and precompiled/preplaced libraries. But then I would not know if that is about the tools or the Arm designs. And distribution of netlists I know nothing about. So, for the Arduino, Raspberry Pi maker market I guess there’s source code in VHDL, Verilog or SystemVerlog that are distributed?

I asked Arm about this, and they answered the following. In short, the deliverable is «soft IP»:

The actual deliverable for such Design start FPGA requests for Arm Cortex M1 and Cortex M3 processors would be soft IP (proposed system with IP protection) that’s publicly available for developers to try our processor cores (not intended for commercial purposes). Combining the performance of a hard CPU with the flexibility of a soft CPU and programmable logic on Xilinx Zynq.

myStorm forum

yosys tagged threads at StackExchange

Some other boards

iCE40 boards

See Clifford Wolf’s chapter iCE40 Boards at [26]. There also is a list of iCE40 Development Boards in Clifford’s lecture, 29.06 into [25].

Lattice iCEstick evaluation kit

See iCEstick Evaluation Kit. This is also mentioned at 9.18 into Clifford Wolf’s lecture [25].

Simon Monk’s book

This book is already mentioned (and the ref is at [13]). The boards he covers are all based on Xilinx chips:

1. Elbert 2. Contains a Xilinx Spartan 3A FPGA and is very cheap. From Numato
2. Mojo. Contains a Xilinx Spartan 6 XC6SLX9 FPGA plus an Atmel ATmega32U4 processor. From Embeddedmicro
3. Papilio. Contains a Xilinx Spartan 6 LX9 FPGA and an Atmel ATmega32U4 processor. From Gadget Factory
4. Other boards mentioned: icoBOARD, Mimas V2

iCEBreaker

There also is this crowdfunded project (on CrowdSupply) called iCEBreaker [19]. It would even have a Pmod driver board for a 64*64 (64×64) LED matrix display. (This was pointed to from this post at the myStorm forum). On 6Nov2019 all these products are on pre-order only.

Pano logic

I was pointed to this by a friend in Nov2019. I think this is a summary:

Pano logic (Wikipedia) was a company that produced thin clients based on FPGAs from Xilinx, containing no CPU. The company shut down in 2012, so http://www.panologic.com is dead. Since then the technology has been reverse engineered (github by twj42 and github by tomverbeure, Tom Verbeure) so that it’s now possible to buy boards with this technology. There also is an overview on Hackaday (here). Now another company Pano logic (here) sell what they call Zero Client without any CPU. However, that page does not seem to have been updated since 2012, so I don’t know.

I just put this up for reference. I guess it would be very fun for those who can find a board at eBay («Pano Logic G2 PCBs with Xilinx Spartan 6 XC6SLX100») and who are already experts and who have the rest of their lives to find out of this. I will not pursue this line.

Zynq-7000 boards

«The Zynq-7000 architecture tightly integrates a dual-core, 650 MHz ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic», from here (also ref’ed above)). The internal ADC handles two channels and runs at max 1MSPS.

Arty boards

Some of these are already mentioned (above)

PicoZed

This is a board with Xilinx Zynq-7000 All Programmable (AP) SoC. See http://zedboard.org/product/picozed. It is used for motor control in the NTNU Revolve electric car 2018/2019 project, see https://www.revolve.no.

Enclustra Mercury Z5

This is used for the NTNU Revolve (above) 2019/2020 project. See https://www.enclustra.com/en/products/system-on-chip-modules/mercury-zx5/

Eclypse Z7

I found this article (sponsored by Digilent, a National Instruments company) in IEEE Spectrum: Breaking Down Barriers in FPGA Engineering Speeds up Development – The use of common programming languages in FPGA development opens process up to more developers, leading to faster and simpler processes. They talk about «Zynq 7020 FPGA SoC from Xilinx, which has a fairly complex combination of a dual-core ARM processor with an FPGA fabric.» More name throwing: Eclyspe platform, Python and LabVIEW.

Ultrascale+

Update Aug2020: Xilinx’s Zynq UltraScale+ MPSoC devices provide 64-bit processor scalability. Compared to the Zynq series, this architecture also contains an inter processor messaging mechanism. Seen from my desk I’d like to see how close these are to to XMOS channels. Interesting. But I read that the Ultrascale+ has less library support than the Zynq-7000.

QMTECH Xilinx

Update 12Feb2024. A friend told me he had used QMTECH Xilinx FPGA Kintex7 Kintex-7 XC7K325T DDR3 Core Board for his new projects. It looks surprisingly well priced. He uses VHDL. He wanted me to add that «the free Vivado ML Standard Edition doesn’t include this device» and that «the board will not be shipped from here to Germany/Austria (maybe whole EU). We arranged out last acquirement via a friend in Switzerland.» Finally «it should be possible to use this device with the old but free (registration required) ISE 14.7 ISE Embedded Edition license.»

Misc

MATLAB/Simulink

See [29].

Avalon interface

Update Sep2021. I found the reference to this in a student paper. Very interesting. I don’t know though, if it’s applicable for this note. This interface deals mostly with synchronous transfer (of course), plus they do have a channel primitive:

5.1. Terms and Concepts: Avalon Streaming System, Avalon Streaming Components, Source and Sink Interfaces and Connections, Backpressure, Transfers and Ready Cycles, Symbol, Channel — A channel is a physical or logical path or link through which information passes between two ports, Beat, Packet.

See [30].

Scratchpad 2

Tiny Tapeout

Thanks to Matt Venn for helping me trying to straighten up this chapter. However, since I start at blank here, all inaccuracies left are on me.

A rather new (to me at least, 2.2024) open source tool is Tiny Tapeout (TinyTapeout), see [32]. With it one can build digital, (and in beta) analogue or mixed systems on an ASIC. It’s «from FPGA to ASIC«.

They collect several projects and have one ASIC produced since each chip has a huge NRE cost. They use the MPW (multi project wafer) service provided by Efabless [34]. So Efabless take 40 different chip designs and put them on one wafer, run 10 wafers and then Tiny Tapeout gets 100 identical parts. The input tool may be a digital design and simulator GUI (Wokwi [35]), Verilog, VHDL or Amaranth [33]. Any tool as long as it produces Verilog in the end. On the [32] top video Matt Venn says that «all our learning resources and tools are free to use and they are online to avoid download installation and licensing problems.» I don’t need to download any tools.

However, if I really want to, I can copy what Tiny Tapeout do with the GitHub action on a local machine by installing all the tools. The OSS CAD Suite (oss-cad-suite) tools are useful for testing the design on an FPGA but aren’t required. The «OSS CAD Suite is a component of YosysHQ’s Tabby CAD Suite«. IceStorm also is a tool in a group there. It looks like I can run this on macOS (Darwin, Arm64 and X64) plus then of course Linux. The source code is also available, should one want to participate.

• Efabless have a shuttle service called an MPW  (multi project wafer). They aggregate 40 designs (=slots) onto one maskset and run enough wafers for each designer to receive 100 chips. And that is used in photolithography to expose all 40 designs at once, multiple times onto a single wafer. The cost to take part in the MPW with a slot is some $10k
  • Tiny Tapeout buys one slot for that amount and receives 100 identical chips
    • They had put ~500 designs inside that one chip design
      • Efabless provide cut out parts from that chip in QFN (quad-flat no-leads) packages, so Tiny Tapeout just have to send them to their PCB manufacturer who mounts the chips onto demonstration boards
        • One demonstration board for each customer

All designs ever done are open for everybody to learn from.

There also is a Discord community chat for help.

Pricing (Feb2024): «160 x 100 um tile + ASIC + demonstration board: The standard price is $300 plus shipping.» [32]. I then would get my one chip mounted on a board.

Clash (HDL)

From [36] I read that:

«Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. It provides a familiar structural design approach to both combinational and synchronous sequential circuits. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Clash is an open-source project, licensed under the permissive BSD2 license, and actively maintained by QBayLogic. The Clash project is a Haskell Foundation affiliated project.»

Very interesting indeed! (TODO: learn more! How about acquiring the book «Retrocomputing with Clash«?)

References

Wiki-refs: ABEL, Discourse, Electronic design automation EDA, FPGA, Lookup table LUT, pip, PLD/PAL, SystemVerilog, Transputer, VHDL, Verilog, Flat no-leads package (QNF, DFN)

1. FPGA Vs ASIC: Differences Between Them And Which One To Use? by Rohit Singh (2018), see https://numato.com/blog/differences-between-fpga-and-asics/
2. myStorm news, events and developments by Folknology, see https://mystorm.uk
3. Principles of CMOS VLSI Design: A Systems Perspective by N. Weste and Kamram Eshraghian, see https://easyengineering.net/principles-of-cmos-vlsi-design-a-systems-perspective-by-weste/
4. Folknology Labs, see https://folknologylabs.wordpress.com
5. IceCore Ice40 HX based modular core by folknology, see https://github.com/folknology/IceCore
6. BlackIce Mx at Tindie shop, see https://www.tindie.com/stores/Folknology/ and https://www.tindie.com/products/Folknology/blackice-mx/
7. Yosys is a framework for Verilog RTL synthesis by Clifford Wolf (cliffordwolf), see http://www.clifford.at/yosys/
   * Documentation: «Yosys Open SYnthesis Suite», see http://www.clifford.at/yosys/documentation.html
   * Only a small subset of SystemVerilog is supported. But there is something called Verific that does more SystemVerilog
   * Also see the IceStorm ref. [26]
   * Observe that there also is a Yosys discussion at StackOverflow [27]
8. STM32 32-bit Arm Cortex MCUs, see https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
9. iCE40 LP/HX/LM Instant mobile innovation that won’t break the bank by Lattice semiconductor, see http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40. Even if iCE40 (with a lower case starting ‘i’) is Lattice style, I also see ICE40, ice40 and Ice40 being used (the latter mostly used in this note)
10. New Product – BlackIce Mx, annoncement by Folknology, see https://forum.mystorm.uk/t/new-product-blackice-mx/551 (starting Apr2019). A thread from the forum:
11. myStorm forum, see https://forum.mystorm.uk. I am now a member: Aclassifier as always. It is not a terribly big forum (about 250 people and 10 new topics the first three weeks of October 2019). But my first topic was solved quite fast. That’s what forums are for.
    – The forum’s SW is the best I have seen. It is Discourse (I found it in the sources, in an invisible footer), made by Jeff Atwood. Easy to use, flexibility, live preview and how it rewards small actions: great! Atwood also co-founded StackOverflow and StackExchange
12. IceCore Getting started, see https://github.com/folknology/IceCore/wiki/IceCore-Getting-Started
13. Programming FPGAs: Getting Started with Verilog (Tab) by Simon Monk (2016), see Amazon. «This hands-on guide is for makers who have been working with Raspberry Pi or Arduino and want to take their projects to the next level with Field Programmable Gate Arrays (FPGAs) and Verilog. Electronics guru Simon Monk follows his best-selling approach―assuming very little, starting slowly with easy, DIY examples, and gradually introducing more complex ideas.» So should fit me! Even if I do have worked with XMOS boards 99.999% of the time. Also see [14]:
14. Using the Programming FPGAs book with IceStorm and myStorm BlackIce by Ed Brindley (2018), see https://maidavale.org/blog/using-simon-monks-programming-fpgas-book-with-icestorm/
15. Verilog vs. VHDL – What to Choose? by hardwarebee (2019) see http://hardwarebee.com/verilog-vs-vhdl-what-to-choose/
16. apio is an open source ecosystem for open FPGA boards, see https://pypi.org/project/apio/
17. BlackIce wiki, see https://github.com/mystorm-org/BlackIce-II/wiki/PLLs
18. BlackIce Mx eBook by Lawrie Griffiths (@lawrie, 2019), starting at Blackice Mx ebook at myStorm forum. The book is at https://lawrie.github.io/blackicemxbook/
19. iCEBreaker FPGA, see https://www.crowdsupply.com/1bitsquared/icebreaker-fpga
20. Digilent Pmod™ ( Interface Specification, Revision: November 20, 201, see http://digilentinc.com/Pmods/Digilent-Pmod_%20Interface_Specification.pdf plus the the Wikipedia article Pmod interface
21. BlackIceMx carrier/connection board, by @folknology, see https://github.com/folknology/BlackIceMx
22. BlackEdge standard by Alan Wood @folknology, see https://github.com/folknology/BlackEdge
23. MixMods proposing document: BlackEdge, my* and mixed signal interfacing support, by Alan Wood @folknology, see https://forum.mystorm.uk/t/blackedge-my-and-mixed-signal-interfacing-support/530
24. BlackIce II Pmod pinouts, started by @uXe, see BlackIce II Pmod pinouts
25. Clifford: A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs at 32nd Chaos Communication Congress (32C3) in Dec2015, by Clifford Wolf, see https://youtu.be/SOn0g3k0FlE (YouTube). Observe that some of the HW he mentions there may not be updated as of Dec2019 (when I write this)
    * Yosys takes input from Verilog. «Verilog is pretty much everything from Verilog 2005»
26. Project IceStorm by Clifford Wolf, see http://www.clifford.at/icestorm/. Based on research by Mathias Lasser and Clifford Wolf. This is the basis of the Yosys tool, also developed by Wolf [7]
27. Yosys discussions at StackOverflow, tagged yosys, see https://stackoverflow.com/questions/tagged/yosys
28. nextpnr — a portable FPGA place and route tool by David Shah, (NextPNR) – next (after arachne-pnr? See https://github.com/YosysHQ/nextpnr. Observe that it also has a gui, do nextpnr-ice40 --gui. Also see Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs by David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanović. See https://arxiv.org/abs/1903.10407
29. Using Simulink to Deploy a MATLAB Algorithm on an FPGA or ASIC by Jack Erickson, MathWorks, see https://www.mathworks.com/videos/using-simulink-to-deploy-a-matlab-algorithm-on-an-fpga-or-asic-1484667134277.html
30. Avalon® Interface Specifications. Updated for Intel® Quartus® Prime Design Suite: 20.1. See https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf?language=en_US
31. 11 Reasons You Should NOT use an FPGA for a Design, and Four Reasons You Should, by Steven Leibson, in EEJournal (20Sep2021). See https://www.eejournal.com/article/11-reasons-you-should-not-use-an-fpga-for-a-design-and-four-reasons-you-should/#comment-79721
32. Tiny Tapeout (TinyTapeout), see https://tinytapeout.com. By Matt Venn (contact)
33. Amaranth, «A modern hardware definition language and toolchain based on Python», see https://github.com/amaranth-lang/amaranth
34. efabless, see https://efabless.com
35. WOKWI, «Simulate IoT Projects in Your Browser» by CodeMagic LTD, see https://wokwi.com
36. Clash. A modern, functional, hardware description language, see https://clash-lang.org